Distributed data-retention power gating techniques for column and row Co-controlled embedded SRAM

Chung Hsien Hua*, Tung Shuan Cheng, Wei Hwang

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

23 Scopus citations

Abstract

In this paper, multi-mode data-retention power gating (P.G.) techniques are presented for embedded memories. These data retention power gating techniques are applied to embedded SRAM with distributed column and row co-controlled capabilities .The SRAM array is divided into blocks. Each block has a dedicated data-retention power gating device. The data-retention power gating devices are controlled by signals from both row and column decoders. Only the selected block is powered-on. Multi-mode power gating structures proposed in this paper can provide 2X to 20X memory cell leakage reduction while maintaining good static noise margin. Simulation results show that for a 64-bit wordline, the active power reductions for 32-bit, 16-bit, and 8-bit blocks are 59%, 79%, and 94%, respectively. All the simulations and physical layout are implemented in TSMC CMOS technology.

Original languageEnglish
Title of host publicationProceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005
Pages129-134
Number of pages6
DOIs
StatePublished - 9 Dec 2005
EventProceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005 - Taipei, Taiwan
Duration: 3 Aug 20055 Aug 2005

Publication series

NameRecords of the IEEE International Workshop on Memory Technology, Design and Testing
ISSN (Print)1087-4852

Conference

ConferenceProceedings - 2005 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2005
CountryTaiwan
CityTaipei
Period3/08/055/08/05

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