Discrete-dopant-induced timing fluctuation and suppression in nanoscale CMOS circuit

Yiming Li*, Chih Hong Hwang, Tien Yeh Li

*Corresponding author for this work

Research output: Contribution to journalArticle

18 Scopus citations

Abstract

As the dimensions of semiconductor devices continue to be reduced, device fluctuations have become critical to determining the accuracy of timing in circuits and systems. This brief studies the discrete-dopant-induced timing characteristic fluctuations in 16-nm-gate complementary metal-oxide-semiconductor (CMOS) circuits using a 3-D "atomistic" coupled device-circuit simulation. The accuracy of the simulation has been confirmed by using the experimentally calibrated transistor physical model. For a 16-nm-gate CMOS inverter, 3.5%, 2.4%, 18.3%, and 13.2% normalized fluctuations in the rise time, fall time, high-to-low delay time, and low-to-high delay time, respectively, are found. Random dopants may cause significant timing fluctuations in the studied circuits. Suppression approaches that are based on the circuit and device design viewpoints are implemented to examine the associated characteristic fluctuations. The use of shunted transistors in the circuit provides similar suppression to the use of a device with doubled width. However, both approaches increase the chip area. To eliminate the need to increase the chip area, channel engineering approaches (vertical and lateral) are proposed, and their effectiveness in reducing the timing fluctuation is demonstrated.

Original languageEnglish
Pages (from-to)379-383
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume56
Issue number5
DOIs
StatePublished - 2009

Keywords

  • Fluctuation suppression technique
  • Modeling and simulation
  • Nanometer-scale metal-oxide-semiconductor field-effect transistor (MOSFET) device and circuit
  • Random dopant effect
  • Timing fluctuation

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