Discrete-dopant-induced power-delay characteristic fluctuation in 16nm complementary metal-oxide-semiconductor with high dielectric constant material

Ming Hung Han*, Yiming Li, Chih Hong Hwang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

In this work, we carry out an experimental validated three-dimensional "atomistic" device-circuit coupled simulation to study the discrete-dopantinduced power and delay fluctuations in 16-nm-gate complementary metal-oxide-semiconductor (CMOS) circuits. The equivalent gate oxide thicknesses (EOTs) of planar CMOS range from 1.2nm to 0.2 nm. SiO2 is used at gate oxide thicknesses of 1.2 and 0.8 nm, Al2O3 at an EOT of 0.4 nm, and HfO2 at an EOT of 0.2 nm. Under the same device threshold voltage, as EOT decreases from 1.2 to 0.2 nm, the fluctuations of threshold voltage and gate capacitance for CMOS transistors are reduced by 43 and 55%, respectively. For the state-of-art nanoscale circuits using high-dielectric constant (high-κ) materials, the delay time fluctuation is suppressed significantly from 0.1 to 0.03 ps. For the powercharacteristics, although the nominal powers of circuits using high-dielectrics are increased owing to the increased EOT, the fluctuations of dynamic power, short circuit power, and static power are reduced by 40, 70, and 30%, respectively.

Original languageEnglish
Article number04DC02
JournalJapanese journal of applied physics
Volume49
Issue number4 PART 2
DOIs
StatePublished - Apr 2010

Fingerprint Dive into the research topics of 'Discrete-dopant-induced power-delay characteristic fluctuation in 16nm complementary metal-oxide-semiconductor with high dielectric constant material'. Together they form a unique fingerprint.

Cite this