Discrete dopant fluctuations in 20-nm/15-nm-gate planar CMOS

Yi-Ming Li*, Shao Ming Yu, Jiunn Ren Hwang, Fu Liang Yang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

105 Scopus citations


We experimentally quantified, for the first time, the random dopant distribution (RDD)-induced threshold voltage Vt standard deviation up to 40 mV for 20-nm-gate planar complementary metal-oxide-semiconductor (CMOS) field-effect transistors. Discrete dopants have been statistically positioned in the 3-D channel region to examine the associated carrier transportation characteristics, concurrently capturing "dopant concentration variation"and "dopant position fluctuation."As the gate length further scales down to 15 nm, the newly developed discrete dopant scheme features an effective solution to suppress the 3-sigma-edge single-digit dopant-induced Vt variation by the gate work function modulation. The results of this paper may postpone the scaling limit projected for planar CMOS.

Original languageEnglish
Pages (from-to)1449-1455
Number of pages7
JournalIEEE Transactions on Electron Devices
Issue number6
StatePublished - Jun 2008


  • 3-D modeling and simulation
  • Complementary metal-oxide-semiconductor (CMOS) device
  • Dopant concentration variation
  • Dopant position fluctuation
  • Random dopant distribution (RDD)
  • Threshold voltage fluctuation

Fingerprint Dive into the research topics of 'Discrete dopant fluctuations in 20-nm/15-nm-gate planar CMOS'. Together they form a unique fingerprint.

Cite this