Direct tunneling RAM (DT-RAM) for high-density memory applications

Charles Kuo*, Tsu Jae King, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalLetterpeer-review

3 Scopus citations

Abstract

A new approach to reducing the tunnel oxide thickness in floating gate memories is introduced for RAM applications. Experimental measurements and two-dimensional (2-D) device simulations are used to investigate the operating principles of a direct tunneling RAM (DT-RAM) cell. DT-RAM targets memory applications in which manufacturability, scalability, low-power, high-density, and long retention times are important considerations.

Original languageEnglish
Pages (from-to)475-477
Number of pages3
JournalIEEE Electron Device Letters
Volume24
Issue number7
DOIs
StatePublished - 1 Jul 2003

Keywords

  • CMOS
  • Data retention time
  • DRAM
  • Embedded DRAM
  • Random access memories
  • Scaling

Fingerprint Dive into the research topics of 'Direct tunneling RAM (DT-RAM) for high-density memory applications'. Together they form a unique fingerprint.

Cite this