Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric

Yee Chia Yeo, Qiang Lu, Wen Chin Lee, Tsu Jae King, Chen-Ming Hu, Xiewen Wang, Xin Guo, T. P. Ma

Research output: Contribution to journalArticlepeer-review

145 Scopus citations

Abstract

We present a study on the characterization and modeling of direct tunneling gate leakage current in both N- and P-type MOSFETs with ultrathin silicon nitride (Si3N4) gate dielectric formed by the jet-vapor deposition (JVD) technique. The tunneling mechanisms in the N- and PMOSFETs were clarified. The electron and hole tunneling masses and barrier potentials for the different tunneling mechanisms were extracted from measured data using a new semi-empirical model. This model was used to project the scaling limits of the JVD Si3N4 gate dielectric based on the supply voltages for the various technology nodes and the maximum tolerable direct tunneling gate current for high-performance and low-power applications.

Original languageEnglish
Pages (from-to)540-542
Number of pages3
JournalIEEE Electron Device Letters
Volume21
Issue number11
DOIs
StatePublished - 1 Nov 2000

Fingerprint Dive into the research topics of 'Direct tunneling gate leakage current in transistors with ultrathin silicon nitride gate dielectric'. Together they form a unique fingerprint.

Cite this