Direct digital frequency synthesis based on a two-level table-lookup scheme

Sau-Gee Chen*, Jen Chuan Chih, Jun Yi Chou

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

In this work, a new direct digital frequency synthesizer (DDFS) is proposed, which is based on a new two-level table-lookup (TLTL) scheme combined with Taylor's expansion. This method only needs a lookup-table size of total n × 2n/4+1 +(n/4-2)× 2n/4 bits, one (n + 1)× 3n/4-bit multiplier, one n∈×∈3n/4-bit multiplier and two additional smaller multipliers, to generate both sine and cosine values (where n is the output precision). Compared with several notable DDFS's, the new design has a smaller lookup-table size and higher SFDR (Spurious Free Dynamic Range) for high-precision output cases, at comparable multiplier and adder complexities. The DDFS is verified by FPGA and EDA tools using Synopsys Design Analyzer and UMC 0.25 μm cell library, assuming 16-bit output precision. The designed 16-bit DDFS has a small gate count of 2,797, and a high SFDR of 110 dBc.

Original languageEnglish
Pages (from-to)153-160
Number of pages8
JournalJournal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
Volume45
Issue number3
DOIs
StatePublished - 1 Dec 2006

Keywords

  • DDFS algorithm
  • Direct digital frequency synthesizer
  • Two-level table lookup scheme

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