Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor

Wen Jie Tsou; Wen Hau Yang; Jian He Lin; Hsin Chen; Ke-Horng Chen; Chin Long Wey; Ying Hsi Lin; Shian Ru Lin; Tsung Yen Tsai

doi:10.1109/ISSCC.2017.7870399

Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor

Wen Jie Tsou, Wen Hau Yang, Jian He Lin, Hsin Chen, Ke-Horng Chen, Chin Long Wey, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

25 Scopus citations

Abstract

Multicore processors have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. In Fig. 20.2.1, high-bandwidth digital low-dropout (DLDO) regulators are used to achieve fast, cost-effective, and energy-efficient functions for on-chip power domains. Nowadays, processor vendors provide software for DVS, allowing the processor to scale the V_OUT to the desired operating-performance point (OPP). However, the DLDO produces an undesirable output voltage ripple ΔV_OUT due to process, voltage, and temperature (PVT) variations. More specifically, the DLDO has a current quantization error (CQE), which depends on the drive current of the least significant bit (LSB) switch in power MOSFET array. PVT variations produce changes in the CQE resulting in different ΔV_OUT at different OPPs. This paper presents a DLDO regulator with an anti-PVT-variation technique permitting tradeoffs among the output voltage ripple, transient performance and load regulation. Experimental results show that the proposed DLDO regulator achieves less than 3mV output ripple ΔV_OUT, while T ranges from 0-80°C and V_OUT ranges from 0.6-1V in steady state, and the transient response time is 1.3μs in case of a load step from 1mA to 201mA.

Original language	English
Title of host publication	2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
Editors	Laura C. Fujino
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	338-339
Number of pages	2
ISBN (Electronic)	9781509037575
DOIs	https://doi.org/10.1109/ISSCC.2017.7870399
State	Published - 2 Mar 2017
Event	64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States Duration: 5 Feb 2017 → 9 Feb 2017

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	60
ISSN (Print)	0193-6530

Conference

Conference	64th IEEE International Solid-State Circuits Conference, ISSCC 2017
Country	United States
City	San Francisco
Period	5/02/17 → 9/02/17

Access to Document

10.1109/ISSCC.2017.7870399

Link to publication in Scopus

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Tsou, W. J., Yang, W. H., Lin, J. H., Chen, H., Chen, K-H., Wey, C. L., Lin, Y. H., Lin, S. R., & Tsai, T. Y. (2017). Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor. In L. C. Fujino (Ed.), 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017 (pp. 338-339). [7870399] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 60). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2017.7870399

Tsou, Wen Jie ; Yang, Wen Hau ; Lin, Jian He ; Chen, Hsin ; Chen, Ke-Horng ; Wey, Chin Long ; Lin, Ying Hsi ; Lin, Shian Ru ; Tsai, Tsung Yen. / Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor. 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. editor / Laura C. Fujino. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 338-339 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{52e1b01d60414c00b1bedfa46e8961f5,

title = "Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor",

abstract = "Multicore processors have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. In Fig. 20.2.1, high-bandwidth digital low-dropout (DLDO) regulators are used to achieve fast, cost-effective, and energy-efficient functions for on-chip power domains. Nowadays, processor vendors provide software for DVS, allowing the processor to scale the VOUT to the desired operating-performance point (OPP). However, the DLDO produces an undesirable output voltage ripple ΔVOUT due to process, voltage, and temperature (PVT) variations. More specifically, the DLDO has a current quantization error (CQE), which depends on the drive current of the least significant bit (LSB) switch in power MOSFET array. PVT variations produce changes in the CQE resulting in different ΔVOUT at different OPPs. This paper presents a DLDO regulator with an anti-PVT-variation technique permitting tradeoffs among the output voltage ripple, transient performance and load regulation. Experimental results show that the proposed DLDO regulator achieves less than 3mV output ripple ΔVOUT, while T ranges from 0-80°C and VOUT ranges from 0.6-1V in steady state, and the transient response time is 1.3μs in case of a load step from 1mA to 201mA.",

author = "Tsou, {Wen Jie} and Yang, {Wen Hau} and Lin, {Jian He} and Hsin Chen and Ke-Horng Chen and Wey, {Chin Long} and Lin, {Ying Hsi} and Lin, {Shian Ru} and Tsai, {Tsung Yen}",

year = "2017",

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doi = "10.1109/ISSCC.2017.7870399",

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Tsou, WJ, Yang, WH, Lin, JH, Chen, H, Chen, K-H, Wey, CL, Lin, YH, Lin, SR & Tsai, TY 2017, Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor. in LC Fujino (ed.), 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017., 7870399, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 60, Institute of Electrical and Electronics Engineers Inc., pp. 338-339, 64th IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, United States, 5/02/17. https://doi.org/10.1109/ISSCC.2017.7870399

Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor. / Tsou, Wen Jie; Yang, Wen Hau; Lin, Jian He; Chen, Hsin; Chen, Ke-Horng; Wey, Chin Long; Lin, Ying Hsi; Lin, Shian Ru; Tsai, Tsung Yen.

2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. ed. / Laura C. Fujino. Institute of Electrical and Electronics Engineers Inc., 2017. p. 338-339 7870399 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 60).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor

AU - Tsou, Wen Jie

AU - Yang, Wen Hau

AU - Lin, Jian He

AU - Chen, Hsin

AU - Chen, Ke-Horng

AU - Wey, Chin Long

AU - Lin, Ying Hsi

AU - Lin, Shian Ru

AU - Tsai, Tsung Yen

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N2 - Multicore processors have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. In Fig. 20.2.1, high-bandwidth digital low-dropout (DLDO) regulators are used to achieve fast, cost-effective, and energy-efficient functions for on-chip power domains. Nowadays, processor vendors provide software for DVS, allowing the processor to scale the VOUT to the desired operating-performance point (OPP). However, the DLDO produces an undesirable output voltage ripple ΔVOUT due to process, voltage, and temperature (PVT) variations. More specifically, the DLDO has a current quantization error (CQE), which depends on the drive current of the least significant bit (LSB) switch in power MOSFET array. PVT variations produce changes in the CQE resulting in different ΔVOUT at different OPPs. This paper presents a DLDO regulator with an anti-PVT-variation technique permitting tradeoffs among the output voltage ripple, transient performance and load regulation. Experimental results show that the proposed DLDO regulator achieves less than 3mV output ripple ΔVOUT, while T ranges from 0-80°C and VOUT ranges from 0.6-1V in steady state, and the transient response time is 1.3μs in case of a load step from 1mA to 201mA.

AB - Multicore processors have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. In Fig. 20.2.1, high-bandwidth digital low-dropout (DLDO) regulators are used to achieve fast, cost-effective, and energy-efficient functions for on-chip power domains. Nowadays, processor vendors provide software for DVS, allowing the processor to scale the VOUT to the desired operating-performance point (OPP). However, the DLDO produces an undesirable output voltage ripple ΔVOUT due to process, voltage, and temperature (PVT) variations. More specifically, the DLDO has a current quantization error (CQE), which depends on the drive current of the least significant bit (LSB) switch in power MOSFET array. PVT variations produce changes in the CQE resulting in different ΔVOUT at different OPPs. This paper presents a DLDO regulator with an anti-PVT-variation technique permitting tradeoffs among the output voltage ripple, transient performance and load regulation. Experimental results show that the proposed DLDO regulator achieves less than 3mV output ripple ΔVOUT, while T ranges from 0-80°C and VOUT ranges from 0.6-1V in steady state, and the transient response time is 1.3μs in case of a load step from 1mA to 201mA.

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Tsou WJ, Yang WH, Lin JH, Chen H, Chen K-H, Wey CL et al. Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor. In Fujino LC, editor, 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 338-339. 7870399. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2017.7870399