Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processor

Wen Jie Tsou, Wen Hau Yang, Jian He Lin, Hsin Chen, Ke-Horng Chen, Chin Long Wey, Ying Hsi Lin, Shian Ru Lin, Tsung Yen Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

25 Scopus citations

Abstract

Multicore processors have been widely used in battery-operated portable systems, desktop, and server applications, where dynamic voltage scaling (DVS) and adaptive voltage scaling (AVS) techniques are commonly employed to lower power consumption and improve thermal performance of the cores. In Fig. 20.2.1, high-bandwidth digital low-dropout (DLDO) regulators are used to achieve fast, cost-effective, and energy-efficient functions for on-chip power domains. Nowadays, processor vendors provide software for DVS, allowing the processor to scale the VOUT to the desired operating-performance point (OPP). However, the DLDO produces an undesirable output voltage ripple ΔVOUT due to process, voltage, and temperature (PVT) variations. More specifically, the DLDO has a current quantization error (CQE), which depends on the drive current of the least significant bit (LSB) switch in power MOSFET array. PVT variations produce changes in the CQE resulting in different ΔVOUT at different OPPs. This paper presents a DLDO regulator with an anti-PVT-variation technique permitting tradeoffs among the output voltage ripple, transient performance and load regulation. Experimental results show that the proposed DLDO regulator achieves less than 3mV output ripple ΔVOUT, while T ranges from 0-80°C and VOUT ranges from 0.6-1V in steady state, and the transient response time is 1.3μs in case of a load step from 1mA to 201mA.

Original languageEnglish
Title of host publication2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
EditorsLaura C. Fujino
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages338-339
Number of pages2
ISBN (Electronic)9781509037575
DOIs
StatePublished - 2 Mar 2017
Event64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States
Duration: 5 Feb 20179 Feb 2017

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume60
ISSN (Print)0193-6530

Conference

Conference64th IEEE International Solid-State Circuits Conference, ISSCC 2017
CountryUnited States
CitySan Francisco
Period5/02/179/02/17

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