Differential cascode voltage switch with the pass-gate (DCVSPG) logic tree for high performance CMOS digital systems

F. S. Lai, W. Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

21 Scopus citations

Abstract

A new circuit configuration, the differential cascode voltage switch with the pass-gate logic tree (DCVSPG), is presented. In this circuit family, we use the pass-gate logic tree to replace the nMOS logic tree in the conventional DCVS circuit in orderto eliminate the floating-node problem. By eliminating the floating-node, the DCVSPG shows superior performance, silicon area and power consumption. Moreover, the dynamic DCVSPG also provides the leverage of relieving the charge redistribution concern and reinforces the signal integrity in the typical pre-charge dynamic circuits. The principle of operation of the DCVSPG is explained. A simple synthesis technique of the pass-gate logic tree is discussed. Finally, a 64-bit carry look-ahead adder is designed by using ths static DCVSPG circuit. A nominal cycle time (Ta = 22°C and power supply of 2.5 V) of 2.0 ns is obtained by using a 0.5μm CMOS technology.

Original languageEnglish
Title of host publication1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Proceedings of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages358-362
Number of pages5
ISBN (Electronic)0780309782
DOIs
StatePublished - 1 Jan 1993
Event1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993 - Taipei, Taiwan
Duration: 12 May 199314 May 1993

Publication series

NameInternational Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)1930-8868

Conference

Conference1993 International Symposium on VLSI Technology, Systems, and Applications, VLSI-TSA 1993
CountryTaiwan
CityTaipei
Period12/05/9314/05/93

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