Different approaches for reliability enhancement of p-channel flash memory

Steve S. Chung, Y. J. Chen, H. W. Tsai

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


In this paper, we will demonstrate two different strategies for designing p-channel flash memories, for achieving better reliability, in particular data retention and drain-disturb. The first one is by using a gate-engineering approach and the other one is using a newly developed substrate bias enhanced Avalanche Hot Electron (AHE) injection programming scheme. For the former, a p-doped floating gate on both p-channel flash cells can be achieved with superior data retention characteristics as well as a 3-order improvement of the drain disturb. For the latter, it exhibits much higher speed and much lower voltage for programming, and very good drain disturb characteristics.

Original languageEnglish
Article number1315429
Pages (from-to)641-642
Number of pages2
JournalIEEE International Reliability Physics Symposium Proceedings
Issue numberJanuary
StatePublished - 1 Jan 2004
Event42nd Annual IEEE International Reliability Physics Symposium, IRPS 2004 - Phoenix, United States
Duration: 25 Apr 200429 Apr 2004

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