In this paper, we will demonstrate two different strategies for designing p-channel flash memories, for achieving better reliability, in particular data retention and drain-disturb. The first one is by using a gate-engineering approach and the other one is using a newly developed substrate bias enhanced Avalanche Hot Electron (AHE) injection programming scheme. For the former, a p-doped floating gate on both p-channel flash cells can be achieved with superior data retention characteristics as well as a 3-order improvement of the drain disturb. For the latter, it exhibits much higher speed and much lower voltage for programming, and very good drain disturb characteristics.
|Number of pages||2|
|Journal||IEEE International Reliability Physics Symposium Proceedings|
|State||Published - 1 Jan 2004|
|Event||42nd Annual IEEE International Reliability Physics Symposium, IRPS 2004 - Phoenix, United States|
Duration: 25 Apr 2004 → 29 Apr 2004