Device structural effects, spice modeling and circuit evaluation for negative-capacitance fets

Pin Su*, Wei Xiang You

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Employing a hafnium-oxide based ferroelectric compatible with present CMOS gate stack, the negative-capacitance FET (NCFET) [1] has garnered substantial interest as it may enable the supply-voltage/power scaling of logic transistors [2]. Several NCFETs, with 2D (Fig. 1) or short-channel FinFET structures, have been experimentally demonstrated with negligible hysteresis (see, e.g., [3] [4]). With its steep slope and similar current transport mechanism to the MOSFET, the NCFET has become a promising beyond-CMOS device candidate.

Original languageEnglish
Title of host publication2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728109428
DOIs
StatePublished - Apr 2019
Event2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019 - Hsinchu, Taiwan
Duration: 22 Apr 201925 Apr 2019

Publication series

Name2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019

Conference

Conference2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
CountryTaiwan
CityHsinchu
Period22/04/1925/04/19

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