Accurate MOSFET I dsat model including LDD parasitic resistance and channel charge and subthreshold regions, particularly moderate inversion and subthreshold regions that are important for low power electronics, are presented with measurement data. Based on these accurate models, CMOS gate performance and power consumption optimization guidelines are discussed in terms of device T ox , V dd and V t . It predicts that there exists certain T ox value that can minimize the gate delay. Device designs for low power electronics considering trade-offs by varying V dd , T ox and V t are highlighted.
|Number of pages||4|
|State||Published - 1996|
|Event||Proceedings of the 1996 International Symposium on Low Power Electronics and Design - Monterey, CA, USA|
Duration: 12 Aug 1996 → 14 Aug 1996
|Conference||Proceedings of the 1996 International Symposium on Low Power Electronics and Design|
|City||Monterey, CA, USA|
|Period||12/08/96 → 14/08/96|