Device design for low power electronics with accurate deep submicrometer LDD-MOSFET models

Kai Chen*, Yuhua Cheng, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

Abstract

Accurate MOSFET I dsat model including LDD parasitic resistance and channel charge and subthreshold regions, particularly moderate inversion and subthreshold regions that are important for low power electronics, are presented with measurement data. Based on these accurate models, CMOS gate performance and power consumption optimization guidelines are discussed in terms of device T ox , V dd and V t . It predicts that there exists certain T ox value that can minimize the gate delay. Device designs for low power electronics considering trade-offs by varying V dd , T ox and V t are highlighted.

Original languageEnglish
Pages197-200
Number of pages4
StatePublished - 1996
EventProceedings of the 1996 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
Duration: 12 Aug 199614 Aug 1996

Conference

ConferenceProceedings of the 1996 International Symposium on Low Power Electronics and Design
CityMonterey, CA, USA
Period12/08/9614/08/96

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