Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates

Vita Pi Ho Hu, Ming Long Fan, Pin Su, Ching Te Chuang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A comparative analysis of Germanium-on-Insulator FinFET (GeOI FinFET) and Germanium on bulk substrate FinFET (Ge bulk FinFET) at device and circuit level with respect to Si counterparts is presented. GeOI FinFET shows larger leakage current than Ge bulk FinFET due to the parasitic bipolar effect triggered by the band-to-band tunneling (BTBT) leakage. The effectiveness of different dual-Vt technology options including increasing channel doping, increasing gate length and drain-side underlap for leakage reduction is analyzed for GeOI and Ge bulk FinFET circuits and SRAMs. An optimum asymmetric underlap design in SRAM using asymmetric underlap pull-up and access transistors (PUAX-asym) is proposed. GeOI and Ge bulk FinFETs with asymmetric underlap design show significant improvement in leakage-delay performance and stability in logic circuits and SRAM cells.

Original languageEnglish
Title of host publicationProceedings of the 14th International Symposium on Quality Electronic Design, ISQED 2013
Pages347-352
Number of pages6
DOIs
StatePublished - 5 Jul 2013
Event14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, CA, United States
Duration: 4 Mar 20136 Mar 2013

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference14th International Symposium on Quality Electronic Design, ISQED 2013
CountryUnited States
CitySanta Clara, CA
Period4/03/136/03/13

Keywords

  • Band-to-Band Tunneling
  • FinFET
  • Germanium
  • Logic Circuit
  • SRAM

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