In this paper CODECS, a mixed-level circuit and device-simulator, is used to investigate switching gate charge characteristics of an integrated VDMOS structure with a detailed description of the dynamics of the charge inside the structure. It is customary to characterize the switching response of a power device by means of a three-region gate charge characteristic. Our simulations show that a four-region gate charge characteristic better describes the dynamic behavior of the structure. The two interpretations converge when the accumulation charge under the thin oxide over the epitaxial region is significantly larger than the inversion charge in the body region. We also show that terraced gate structures have a gate charge characteristic which is significantly different from the conventional one unless the thin oxide gate region is made considerably larger than the field oxide region. The four-region gate charge characteristic is confirmed for inductive turn-on and turn-off transients parasitic bipolar turn-on is discussed and clamped turn-on results are validated against experimental data. A brief overview of CODECS numerical performance concludes the paper.