Device and technology optimization guidelines for low power design in deep sub-micron regime based on analytical and experimental studies are presented. Fundamental design quantities such as driving current, propagation delay, and switching energy are examined. Empirical driving current equations and device optimization with gate oxide, channel length and power supply scaling as well as interconnect loading are extracted.
|Number of pages||5|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 International Symposium on Low Power Electronics and Design - Monterey, CA, USA|
Duration: 18 Aug 1997 → 20 Aug 1997
|Conference||Proceedings of the 1997 International Symposium on Low Power Electronics and Design|
|City||Monterey, CA, USA|
|Period||18/08/97 → 20/08/97|