Device and technology optimization for low power design in deep sub-micron regime

Kai Chen*, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to conferencePaper

5 Scopus citations

Abstract

Device and technology optimization guidelines for low power design in deep sub-micron regime based on analytical and experimental studies are presented. Fundamental design quantities such as driving current, propagation delay, and switching energy are examined. Empirical driving current equations and device optimization with gate oxide, channel length and power supply scaling as well as interconnect loading are extracted.

Original languageEnglish
Pages312-316
Number of pages5
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 International Symposium on Low Power Electronics and Design - Monterey, CA, USA
Duration: 18 Aug 199720 Aug 1997

Conference

ConferenceProceedings of the 1997 International Symposium on Low Power Electronics and Design
CityMonterey, CA, USA
Period18/08/9720/08/97

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    Chen, K., & Hu, C-M. (1997). Device and technology optimization for low power design in deep sub-micron regime. 312-316. Paper presented at Proceedings of the 1997 International Symposium on Low Power Electronics and Design, Monterey, CA, USA, . https://doi.org/10.1145/263272.263363