Device and circuit level suppression techniques for random-dopant-induced static noise margin fluctuation in 16-nm-gate SRAM cell

Kuo Fu Lee, Yiming Li*, Tien Yen Li, Zhong Cheng Su, Chin Hong Hwang

*Corresponding author for this work

Research output: Contribution to journalArticle

2 Scopus citations

Abstract

In this study, a three-dimensional "atomistic" coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal-oxide-semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are further implemented to examine the associated characteristics in 16-nm-gate SRAM cells. From the circuit viewpoint, the SNM of 8T planar SRAM is enlarged to 230 mV and the variation of SNM (σSNM) is reduced to 22 mV at a cost of 30% extra chip area. As for device level improvement, silicon-on-insulator (SOI) FinFETs replaced the planar MOSFETs in 6T SRAM is further examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the σSNM is suppressed significantly to 5.4 mV. However, development of fabrication process for SOI FinFET SRAM is crucial for sub-22 nm technology era.

Original languageEnglish
Pages (from-to)647-651
Number of pages5
JournalMicroelectronics Reliability
Volume50
Issue number5
DOIs
StatePublished - May 2010

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