Development of a high bandwidth merged logic/DRAM multimedia chip

W. K. Luk*, Y. Katayama, Wei Hwang, M. Wordeman, T. Kirihata, A. Satoh, S. Munetoh, H. Wong, B. El-Kareh, P. Xiao, R. Joshi

*Corresponding author for this work

Research output: Contribution to conferencePaper

4 Scopus citations

Abstract

This paper describes the design methodology and the implementation of a merged logic/DRAM multimedia chip. The design is based on 0.25 micron DRAM-based CMOS technology with 4-layers of metal with device performance enhancement. Details of the architecture and system design of the multi-media was described in [1]. The present chip consists of 64 Mb of synchronous DRAM which is organized in two banks of eight 8 Mb SDRAM macros, a gate-array memory control and bus control unit, a custom-designed 8×32-bit parallel graphic processor, a 64-bit parallel ports for data transfer to/from the host processor bus, a 32-bit serial port for video display, and an on-chip PLL. The multi-media co-processor chip provides high-density unified memory, high bus bandwidth (4.3 GB/s peak) and 1+ GB/s BITBLT processing functions for an external host processor. The current design, floorplan and layout are structured in a way that, we believe, will provide a general framework for other merged logic/DRAM, ASIC+DRAM design for system scale integration.

Original languageEnglish
Pages279-285
Number of pages7
DOIs
StatePublished - 1 Dec 1997
EventProceedings of the 1997 International Conference on Computer Design - Austin, TX, USA
Duration: 12 Oct 199715 Oct 1997

Conference

ConferenceProceedings of the 1997 International Conference on Computer Design
CityAustin, TX, USA
Period12/10/9715/10/97

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    Luk, W. K., Katayama, Y., Hwang, W., Wordeman, M., Kirihata, T., Satoh, A., Munetoh, S., Wong, H., El-Kareh, B., Xiao, P., & Joshi, R. (1997). Development of a high bandwidth merged logic/DRAM multimedia chip. 279-285. Paper presented at Proceedings of the 1997 International Conference on Computer Design, Austin, TX, USA, . https://doi.org/10.1109/ICCD.1997.628880