This paper describes the design methodology and the implementation of a merged logic/DRAM multimedia chip. The design is based on 0.25 micron DRAM-based CMOS technology with 4-layers of metal with device performance enhancement. Details of the architecture and system design of the multi-media was described in . The present chip consists of 64 Mb of synchronous DRAM which is organized in two banks of eight 8 Mb SDRAM macros, a gate-array memory control and bus control unit, a custom-designed 8×32-bit parallel graphic processor, a 64-bit parallel ports for data transfer to/from the host processor bus, a 32-bit serial port for video display, and an on-chip PLL. The multi-media co-processor chip provides high-density unified memory, high bus bandwidth (4.3 GB/s peak) and 1+ GB/s BITBLT processing functions for an external host processor. The current design, floorplan and layout are structured in a way that, we believe, will provide a general framework for other merged logic/DRAM, ASIC+DRAM design for system scale integration.
|Number of pages||7|
|State||Published - 1 Dec 1997|
|Event||Proceedings of the 1997 International Conference on Computer Design - Austin, TX, USA|
Duration: 12 Oct 1997 → 15 Oct 1997
|Conference||Proceedings of the 1997 International Conference on Computer Design|
|City||Austin, TX, USA|
|Period||12/10/97 → 15/10/97|