Development and electrical investigation of through glass via and through si via in 3D integration

Geng Ming Chang, Shih Wei Lee, Ching Yun Chang, Kuan-Neng Chen*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this research, an optimized process scheme for through glass via (TGV)/through silicon via (TSV) fabrication is proposed to solve the difficulty of copper (Cu) filling in TGV/TSV. Kelvin structure, daisy chain, and comb structure are fabricated for evaluating electrical performance. Comparison between TGV and TSV shows that the power loss and overall process steps (cost) of TGV is lower than TSV for 3D interconnect. Moreover, daisy chain structure at chip-level is fabricated and investigated on its reliability including thermal cycling and humidity test. Finally, TGV/TSV without voids and V-shape pits formed at the filler are successfully fabricated and demonstrated at chip-level with 50-μm TGV/TSV and 200-μm thinned wafers.

Original languageEnglish
Title of host publication2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509058051
DOIs
StatePublished - 7 Jun 2017
Event2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 - Hsinchu, Taiwan
Duration: 24 Apr 201727 Apr 2017

Publication series

Name2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

Conference

Conference2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
CountryTaiwan
CityHsinchu
Period24/04/1727/04/17

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