Design techniques for single-low-VDD CMOS systems

Jinn Shyan Wang*, Hung Yu Li, Chingwei Yeh, Tien-Fu Chen

*Corresponding author for this work

Research output: Contribution to journalArticle

13 Scopus citations


In this paper, a new CMOS design scheme called the single-low-V DD CMOS (SLVCMOS) is proposed. With this scheme, a CMOS design implemented in a multi-VTH CMOS technology can be operated with a very low external supply voltage, say 0.5-V, with a sleep current at the level of only picoampere per gate. The key items for a single-chip SLVCMOS design include a sleepless mixed-VTH flip-flop, a boosted sleeping clock signal, and three low-power hard blocks. Analysis shows that additional benefits of using the SLVCMOS include higher performance and lower power consumption in the active mode, smaller leakage current in the sleep mode, shorter wake-up time and reduced wake-up energy during the sleep-to-active transition, and a reduced number of sleep-control signals, saving precious routing resources and reducing the chip area. A dual-rail SLVCMOS cell library and two test chips, one 32-b RISC core and the other verifying the design of hard blocks, are designed and implemented to show the feasibility of the proposed design scheme and the design techniques.

Original languageEnglish
Pages (from-to)1157-1164
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Issue number5
StatePublished - 1 May 2005


  • Cell library
  • Charge pump
  • Flip-flop
  • Low power
  • Low voltage
  • RISC

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