Design optimization of metal nanocrystal memory - Part II: Gate-stack engineering

Tuo-Hung Hou*, Chungho Lee, Verikat Narayanan, Udayan Ganguly, Edwin Chihchuan Kan

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

34 Scopus citations

Abstract

Based on the physical model of nanocrystal (NC) memories described in Part I, a systematic investigation of gate-stack engineering is presented, including high-κ control and tunneling oxides. The high-κ control oxide enables the effective-oxide-thickness scaling without compromising the memory performance, owing to the low charging energy and large channel-control factor from the three-dimensional electrostatics. The high-κ tunneling oxide, on the other hand, improves the retention characteristics utilizing the asymmetric tunneling barrier more effectively away from the direct tunneling regime. Finally, with the optimization strategies introduced in both Parts I and II, a metal NC memory design with 1.0-V memory window, 13-μs programming, 2.5-μs erasing, and over 10-year retention time has been demonstrated at ±4-V operation, which highlights the potential of NC memories as the next-generation nonvolatile memory.

Original languageEnglish
Pages (from-to)3103-3108
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume53
Issue number12
DOIs
StatePublished - 1 Dec 2006

Keywords

  • Electrostatics
  • High-κ dielectrics
  • Modeling
  • Nanocrystal (NC)
  • Nonvolatile memories
  • Three-dimensional (3-D)

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