Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology

Ming-Dou Ker*, Hsin Chin Jiang, Chyh Yih Chang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


A new structure design of bond pad is proposed to reduce its parasitic capacitance in general CMOS processes without extra process modification. The proposed bond pad is constructed by connecting multilayer metals and inserting additional diffusion layers into the substrate below the metal layers. The metal layers except top metal layer are designed with special patterns, which have smaller area than that in the traditional bond pad. Both the additional diffusion layers and patterned metal layers are used to reduce the parasitic capacitance of bond pad. An experimental test chip has been designed and fabricated to investigate the reduction of parasitic capacitance of the bond pad. The bonding reliability tests on the fabricated bond pad, including the ball-shear and wire-pull tests, are also used to verify the bonding adhesion. The experimental results show that the proposed low-capacitance bond pad has a capacitance less than 50% of that in the traditional bond pad. The new proposed bond pads can also keep the same good bonding reliability as that of a traditional bond pad.

Original languageEnglish
Pages (from-to)2953-2956
Number of pages4
JournalIEEE Transactions on Electron Devices
Issue number12
StatePublished - 1 Dec 2001


  • Bond pad
  • High-speed I/O
  • Low capacitance pad
  • Parasitic capacitance

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