Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process

Ming-Dou Ker*, Wen Yi Chen, Kuo Chun Hsu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

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Engineering & Materials Science