Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in A 0.13-μM CMOS technology

Che Hao Chuang*, Ming-Dou Ker

*Corresponding author for this work

Research output: Contribution to journalConference article

28 Scopus citations

Abstract

This paper presents a 1.2V/2.5V tolerant I/O buffer design with only thin gate-oxide devices. The novel floating N-well and gate-tracking circuits in mixed-voltage I/O buffer are proposed to overcome the problem of leakage current, which will occur in the conventional CMOS I/O buffer when using in the mixed-voltage I/O interfaces. The new proposed 1.2V/2.5V tolerant I/O buffer design has been successfully verified in a 0.13-μm salicided CMOS process, which can be also applied in other CMOS processes to serve different mixed-voltage I/O interfaces.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 7 Sep 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 23 May 200426 May 2004

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