Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs

Kun Hsien Lin*, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

12 Scopus citations

Abstract

The holding voltage of the high-voltage ESD protection devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-μm 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with VDD of 40V.

Original languageEnglish
Title of host publication2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04
DOIs
StatePublished - 1 Dec 2004
Event2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04 - Grapevine, TX, United States
Duration: 19 Sep 200423 Sep 2004

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)0739-5159

Conference

Conference2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04
CountryUnited States
CityGrapevine, TX
Period19/09/0423/09/04

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