Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics

Joshi Rajiv V., Mukhopadhyay Saibal, Plass Donald W., Yuan H. Chan, Ching-Te Chuang, Tan Yue

Research output: Contribution to journalArticlepeer-review

25 Scopus citations

Abstract

In this paper we have studied the impacts of floating body effect, device leakage, and gate oxide tunneling leakage on the read and write-ability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100 nm technology for the first time. The floating body effect is shown to degrade the read stability while improving the write-ability. On the other hand, the gate-to-body tunneling current improves the read stability while degrading the write-ability. It is also shown that the use of high-Vt and thick oxide cell transistors can improve leakage, read and write-ability without causing significant performance degradation. The test-chip is fabricated in sub-90 nm SOI technology to show the effectiveness of high-Vt and thick-oxide devices in improving stability of SRAM cells.
Original languageEnglish
Pages (from-to)965-976
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number3
DOIs
StatePublished - Mar 2009

Keywords

  • Dynamic stability; high-Vt; process variation; SRAM; thick oxide; write-ability

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