Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics

Joshi Rajiv V.; Mukhopadhyay Saibal; Plass Donald W.; Yuan H. Chan; Ching-Te Chuang; Tan Yue

doi:10.1109/JSSC.2009.2013768

Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics

Joshi Rajiv V., Mukhopadhyay Saibal, Plass Donald W., Yuan H. Chan, Ching-Te Chuang, Tan Yue

Department of Electronics Engineering

Research output: Contribution to journal › Article › peer-review

25 Scopus citations

Abstract

In this paper we have studied the impacts of floating body effect, device leakage, and gate oxide tunneling leakage on the read and write-ability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100 nm technology for the first time. The floating body effect is shown to degrade the read stability while improving the write-ability. On the other hand, the gate-to-body tunneling current improves the read stability while degrading the write-ability. It is also shown that the use of high-Vt and thick oxide cell transistors can improve leakage, read and write-ability without causing significant performance degradation. The test-chip is fabricated in sub-90 nm SOI technology to show the effectiveness of high-Vt and thick-oxide devices in improving stability of SRAM cells.

Original language	English
Pages (from-to)	965-976
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	44
Issue number	3
DOIs	https://doi.org/10.1109/JSSC.2009.2013768
State	Published - Mar 2009

Keywords

Dynamic stability; high-Vt; process variation; SRAM; thick oxide; write-ability

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title = "Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics",

abstract = "In this paper we have studied the impacts of floating body effect, device leakage, and gate oxide tunneling leakage on the read and write-ability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100 nm technology for the first time. The floating body effect is shown to degrade the read stability while improving the write-ability. On the other hand, the gate-to-body tunneling current improves the read stability while degrading the write-ability. It is also shown that the use of high-Vt and thick oxide cell transistors can improve leakage, read and write-ability without causing significant performance degradation. The test-chip is fabricated in sub-90 nm SOI technology to show the effectiveness of high-Vt and thick-oxide devices in improving stability of SRAM cells.",

keywords = "Dynamic stability; high-Vt; process variation; SRAM; thick oxide; write-ability",

author = "{Rajiv V.}, Joshi and Mukhopadhyay Saibal and {Donald W.}, Plass and Chan, {Yuan H.} and Ching-Te Chuang and Tan Yue",

year = "2009",

month = mar,

doi = "10.1109/JSSC.2009.2013768",

language = "English",

volume = "44",

pages = "965--976",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics

AU - Rajiv V., Joshi

AU - Saibal, Mukhopadhyay

AU - Donald W., Plass

AU - Chan, Yuan H.

AU - Chuang, Ching-Te

AU - Yue, Tan

PY - 2009/3

Y1 - 2009/3

N2 - In this paper we have studied the impacts of floating body effect, device leakage, and gate oxide tunneling leakage on the read and write-ability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100 nm technology for the first time. The floating body effect is shown to degrade the read stability while improving the write-ability. On the other hand, the gate-to-body tunneling current improves the read stability while degrading the write-ability. It is also shown that the use of high-Vt and thick oxide cell transistors can improve leakage, read and write-ability without causing significant performance degradation. The test-chip is fabricated in sub-90 nm SOI technology to show the effectiveness of high-Vt and thick-oxide devices in improving stability of SRAM cells.

AB - In this paper we have studied the impacts of floating body effect, device leakage, and gate oxide tunneling leakage on the read and write-ability of a PD/SOI CMOS SRAM cell under Vt, L and W variations in sub-100 nm technology for the first time. The floating body effect is shown to degrade the read stability while improving the write-ability. On the other hand, the gate-to-body tunneling current improves the read stability while degrading the write-ability. It is also shown that the use of high-Vt and thick oxide cell transistors can improve leakage, read and write-ability without causing significant performance degradation. The test-chip is fabricated in sub-90 nm SOI technology to show the effectiveness of high-Vt and thick-oxide devices in improving stability of SRAM cells.

KW - Dynamic stability; high-Vt; process variation; SRAM; thick oxide; write-ability

U2 - 10.1109/JSSC.2009.2013768

DO - 10.1109/JSSC.2009.2013768

M3 - Article

VL - 44

SP - 965

EP - 976

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

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