Design of mixed-voltage-tolerant crystal oscillator circuit in low-voltage CMOS technology

Tzu Ming Wang*, Ming-Dou Ker, Hung Tai Liao

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

8 Scopus citations

Abstract

In the nanometer-scale CMOS technology, the gateoxide thickness has been scaled down to provide higher operating speed with lower power supply voltage. However, regarding compatibility with the earlier defined standards or interface protocols of CMOS ICs in a microelectronics system, the chips fabricated in the advanced CMOS processes face the gate-oxide reliability problems in the interface circuits due to the voltage levels higher than normal supply voltage (1 × VDD) required by earlier applications. As a result, mixed-voltage I/O circuits realized with only thin-oxide devices had been designed with advantages of less fabrication cost and higher operating speed to communicate with the circuits at different voltage levels. In this paper, two new mixed-voltage-tolerant crystal oscillator circuits realized with low-voltage CMOS devices are proposed without suffering the gate-oxide reliability issues. The proposed mixed-voltage crystal oscillator circuits, which are one of the key I/O cells in a cell library, have been designed and verified in a 90-nm 1-V CMOS process, to serve 1-V/2-V tolerant mixed-voltage interface applications.

Original languageEnglish
Pages (from-to)966-974
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume56
Issue number5
DOIs
StatePublished - 30 Jun 2009

Keywords

  • Crystal oscillator
  • Gate-oxide reliability
  • Mixedvoltage I/O

Fingerprint Dive into the research topics of 'Design of mixed-voltage-tolerant crystal oscillator circuit in low-voltage CMOS technology'. Together they form a unique fingerprint.

Cite this