Design of mixed-voltage I/O buffer by using NMOS-blocking technique

Ming-Dou Ker*, Shih Lun Chen

*Corresponding author for this work

Research output: Contribution to journalArticle

27 Scopus citations

Abstract

An nMOS-blocking technique for mixed-voltage I/O buffer realized with only 1 × V DD devices can receive 2 ×V DD, 3 × V DD, and even 4 × V DD input signal without the gate-oxide reliability issue is proposed. In this paper, the 2 × V DD input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.25-μm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3 × V DD input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.13-μm 1-V CMOS process to serve 1/3-V mixed-voltage interface. The proposed nMOS-blocking technique can be extended to design the 4 × V DD, 5 × V DD, and even 6 × V DD input tolerant mixed-voltage I/O buffers. The limitation of the nMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process.

Original languageEnglish
Article number1703687
Pages (from-to)2324-2333
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number10
DOIs
StatePublished - 1 Oct 2006

Keywords

  • Gate-oxide reliability
  • Hot-carrier degradation
  • Interface
  • Junction breakdown
  • Mixed-voltage I/O buffer

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