Design of memory sub-system in H.264/AVC decoder

Chih Hung Li, Chang Hsuan Chang, Wen-Hsiao Peng, Wei Hwang, Tihao Chiang*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

In this paper, we present the memory sub-system of a H.264/AVC decoder designed for High profile and Level 4. Our design incorporates a synchronization buffer as a pre-cache buffer. We investigate the efficiency of DRAM access and power dissipation when the buffer is designed at different granularities. Statistical results show that the granularity of larger block size has higher memory efficiency, less access cycles and power dissipation. However, the granularity of 8×8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.

Original languageEnglish
Title of host publicationDigest of Technical Papers - 2007 International Conference on Consumer Electronics, ICCE 2007
DOIs
StatePublished - 24 Aug 2007
Event2007 Digest of Technical Papers International Conference on Consumer Electronics - Las Vegas, NV, United States
Duration: 10 Jan 200714 Jan 2007

Publication series

NameDigest of Technical Papers - IEEE International Conference on Consumer Electronics
ISSN (Print)0747-668X

Conference

Conference2007 Digest of Technical Papers International Conference on Consumer Electronics
CountryUnited States
CityLas Vegas, NV
Period10/01/0714/01/07

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  • Cite this

    Li, C. H., Chang, C. H., Peng, W-H., Hwang, W., & Chiang, T. (2007). Design of memory sub-system in H.264/AVC decoder. In Digest of Technical Papers - 2007 International Conference on Consumer Electronics, ICCE 2007 [4146002] (Digest of Technical Papers - IEEE International Conference on Consumer Electronics). https://doi.org/10.1109/ICCE.2007.341382