Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

Po Yen Chiu*, Ming-Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Scopus citations

Abstract

A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25 °C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition.

Original languageEnglish
Title of host publication2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011
DOIs
StatePublished - 24 Jun 2011
Event2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011 - Kaohsiung, Taiwan
Duration: 2 May 20114 May 2011

Publication series

Name2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011

Conference

Conference2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011
CountryTaiwan
CityKaohsiung
Period2/05/114/05/11

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    Chiu, P. Y., & Ker, M-D. (2011). Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process. In 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011 [5783185] (2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011). https://doi.org/10.1109/ICICDT.2011.5783185