Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits

Ming-Dou Ker*, Hsin Chin Jiang, Chyh Yih Chang

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

11 Scopus citations

Abstract

A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.

Original languageEnglish
Pages (from-to)293-296
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
StatePublished - 1 Jan 2000
EventProceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA
Duration: 13 Sep 200016 Sep 2000

Fingerprint Dive into the research topics of 'Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits'. Together they form a unique fingerprint.

Cite this