Design of high-voltage-tolerant ESD protection circuit in low-voltage CMOS processes

Ming-Dou Ker*, Chang Tzu Wang

*Corresponding author for this work

Research output: Contribution to journalArticle

17 Scopus citations

Abstract

Two new electrostatic discharge (ESD) protection design by using only 1 × VDD low-voltage devices for mixed-voltage I/O buffer with 3 × VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD protection designs have been successfully verified in two different 0.13- μm 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers.

Original languageEnglish
Article number4796375
Pages (from-to)49-58
Number of pages10
JournalIEEE Transactions on Device and Materials Reliability
Volume9
Issue number1
DOIs
StatePublished - 16 Mar 2009

Keywords

  • Electrostatic discharge (ESD)
  • Low-voltage CMOS
  • Mixed-voltage I/O
  • Substrate-triggered technique

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