Design of high-performance and highly reliable nMOSFETs with embedded Si:C S/D extension stressor(Si:C S/D-E)

Steve S. Chung, E. R. Hsieh, P. W. Liu, W. T. Chiang, S. H. Tsai, T. L. Tsai, R. M. Huang, C. H. Tsai, W. Y. Teng, C. I. Li, T. F. Kuo, Y. R. Wang, C. L. Yang, C. T. Tsai, G. H. Ma, S. C. Chien, S. W. Sun

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

6 Scopus citations

Abstract

A Novel strained nMOSFET with embedded Si:C in S/D extension stressor (Si:C S/D-E) was presented. Comparing to the bulk device, it revealed good drive current I ON (+27%), high I D,sat current (+67%), enhanced channel mobility (+105%), at a lower effective substitutional carbon concentration (C%=1.1%), using the poly-gate 40nm-node Si:C/eSiGe S/D CMOS technology. Moreover, PBTI effect was first observed in this device as a result of Carbn impurity out-diffusion, which is of critically important for the design trade-off between performance and reliability.

Original languageEnglish
Title of host publication2009 Symposium on VLSI Technology, VLSIT 2009
Pages158-159
Number of pages2
StatePublished - 16 Nov 2009
Event2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan
Duration: 16 Jun 200918 Jun 2009

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Conference

Conference2009 Symposium on VLSI Technology, VLSIT 2009
CountryJapan
CityKyoto
Period16/06/0918/06/09

Keywords

  • CMOS
  • Embedded SiC
  • Positive temperature bias instability
  • Strained technology

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