An 128×128 high-performance CMOS image sensor is designed by using shared-buffer direct injection (SBDI) biasing technique and shared off-focal-plane-array (off-FPA) integration capacitor structure. Each pixel contains only a photodiode and a MOS switch. The pixel size is 30×30 μm2 and can be further shrunk. Due to the new SBDI biasing technique, the linearity and the dynamic range of the CMOS image sensor are increased. The use of shared off-FPA integration capacitor leads to large charge capacity and dynamic range. The CMOS image sensor has charge capacity of 5×107 electrons, transimpedance of 5×108 ohms at 20 nA background current, and power dissipation of 30 mW under 5V power supply. Moreover, the current-mode background suppression and dynamic discharge source follower output stage are proposed to further increase the signal dynamic range and improve the speed performance of output stage. The designed CMOS image sensor is fabricated by 0.5μm double-poly double-metal (DPDM) n-well CMOS technology. The function and performance of the proposed CMOS image sensor have been verified by experimental results.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 1 Jan 1999|
|Event||Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA|
Duration: 30 May 1999 → 2 Jun 1999