Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology

Hun Hsien Chang*, Ming-Dou Ker, Jiin Chuan Wu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

A novel dynamic-floating-gate technique is proposed to improve ESD robustness of the CMOS output buffers with small driving/sinking currents. This dynamic-floating-gate design can effectively solve the ESD protection issue which is due to the different circuit connections on the output devices. By adding suitable time delay to dynamically float the gates of the output NMOS/PMOS devices which are originally unused in the output buffer, the human-body-model (machine-model) ESD failure threshold of a 2-mA output buffer can be practically improved from the original 1.0 kV (100 V) up to greater than 8 kV (1500 V) in a 0.35-μm bulk CMOS process.

Original languageEnglish
Pages (from-to)375-393
Number of pages19
JournalSolid-State Electronics
Volume43
Issue number2
DOIs
StatePublished - 1 Jan 1999

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