Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-μm CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.
|Number of pages||4|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|State||Published - 1 Jan 1997|
|Event||Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA|
Duration: 7 Sep 1997 → 10 Sep 1997