Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique

Ming-Dou Ker*, Tung Yang Chen, Chung-Yu Wu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

15 Scopus citations

Abstract

Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-μm CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.

Original languageEnglish
Pages (from-to)287-290
Number of pages4
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs
StatePublished - 1 Jan 1997
EventProceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA
Duration: 7 Sep 199710 Sep 1997

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