Design of CMOS analog cells for low-voltage VLSI

Chung-Chih Hung*, Changku Hwang, Kari Halonen, Veikko Porra, Mohammed Ismail

*Corresponding author for this work

Research output: Contribution to conferencePaper

Abstract

In this paper, two CMOS analog signal processing circuits which could find wide use in low-voltage VLSI applications are presented. The two circuits include a voltage-to-current converter (V-I converter) and a multiplier. Both of the circuits can operate from rail to rail with a power supply of 3V. They were fabricated in a 2μm N-well double-poly CMOS process by MOSIS. In either of the circuits, an N-type circuit cell is connected in parallel with its P-type counterpart to achieve common-mode rail-to-rail operation. For the V-I converter, a nominal value of a 200μS transconductance with a tuning range of 0.5 to 2 is obtained when the input signal swing is 1 VPP. For the analog multiplier, it is realized by a parallel connection of the two V-I converters. Both of the input signal swings of the multiplier are measured as 1VPP and 1.6VPP, respectively.

Original languageEnglish
Pages15-18
Number of pages4
DOIs
StatePublished - 1 Dec 1996
EventProceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3) - Ames, IA, USA
Duration: 18 Aug 199621 Aug 1996

Conference

ConferenceProceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3)
CityAmes, IA, USA
Period18/08/9621/08/96

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    Hung, C-C., Hwang, C., Halonen, K., Porra, V., & Ismail, M. (1996). Design of CMOS analog cells for low-voltage VLSI. 15-18. Paper presented at Proceedings of the 1996 IEEE 39th Midwest Symposium on Circuits & Systems. Part 3 (of 3), Ames, IA, USA, . https://doi.org/10.1109/MWSCAS.1996.594014