Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

Ming-Dou Ker*, Shih Lun Chen, Chia Shen Tsai

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

167 Scopus citations

Abstract

A new charge pump circuit with consideration of gate-oxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-μm 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.

Original languageEnglish
Pages (from-to)1100-1107
Number of pages8
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number5
DOIs
StatePublished - 1 May 2006

Keywords

  • Body effect
  • Charge pump circuit
  • Gate-oxide reliability
  • High-voltage generator
  • Low voltage

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