Design of application specific throughput processor for matrix operations

Ping Ju Wu, Chien Yu Lin, Bo-Cheng Lai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In modern computation routines, matrix operations are broadly used in many scientific realms, ranging from high performance supercomputers to resource constrained embedded devices. Previous studies have revealed that the computation efficiency of matrix operations is significantly determined by the data accesses behavior of the computation platform. This paper introduces an integrated multicore system, including software stacks and hardware modules that can accelerate matrix operations and reduce data access overhead. With the proposed hardware module, the performance of our multicore embedded platform can improve up to 24.09%. Besides the hardware design, we also develop a framework that can facilitate the prototyping of embedded system designs, including functional verification of hardware modules as well as co-simulation with high level OpenCL language.

Original languageEnglish
Title of host publicationProceedings - 2015 18th International Conference on Network-Based Information Systems, NBiS 2015
EditorsLeonard Barolli, Makoto Takizawa, Fatos Xhafa, Hui-Huang Hsu, Tomoya Enokido
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages324-331
Number of pages8
ISBN (Electronic)9781479999422
DOIs
StatePublished - 9 Dec 2015
Event18th International Conference on Network-Based Information Systems, NBiS 2015 - Taipei, Taiwan
Duration: 2 Sep 20154 Sep 2015

Publication series

NameProceedings - 2015 18th International Conference on Network-Based Information Systems, NBiS 2015

Conference

Conference18th International Conference on Network-Based Information Systems, NBiS 2015
CountryTaiwan
CityTaipei
Period2/09/154/09/15

Keywords

  • Design framework
  • FPGA
  • Matrix operations
  • OpenCL
  • Throughput processor

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