Design of analog pixel memory circuit with low temperature polycrystalline silicon TFTs for low power application

Li Wei Chu*, Po-Tsun Liu, Ming-Dou Ker, Guang Ting Zheng, Yu Hsuan Li, Chung Hung Kuo, Chun Huai Li, Yao Jen Hsieh, Chun Ting Liu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

A new analog pixel memory cell realized in a 3-μm LTPS technology is proposed to achieve low-power consumption for TFT-LCDs. By employing the inversion data in storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60Hz to 3Hz with output decay only less than 0.075V under the input data from IV to 4V.

Original languageEnglish
Title of host publication48th Annual SID Symposium, Seminar, and Exhibition 2010, Display Week 2010
Pages1363-1366
Number of pages4
Volume41
Edition1
DOIs
StatePublished - 1 Dec 2010
Event48th Annual SID Symposium, Seminar, and Exhibition 2010, Display Week 2010 - Seattle, WA, United States
Duration: 23 May 201028 May 2010

Conference

Conference48th Annual SID Symposium, Seminar, and Exhibition 2010, Display Week 2010
CountryUnited States
CitySeattle, WA
Period23/05/1028/05/10

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