This paper presents an all-digital low-voltage-differential-signaling (LVDS) driver design for Serial Advanced Technology Attachment II. A simultaneous-switching-noise reduction technique and an autocalibration mechanism are implemented to suppress switching noise and to handle process and environmental variations. The circuit is implemented in a 0.18-μm 1P6M CMOS process with a core area of 0.072 mm2. At 3 Gbps, it consumes 9 mW of power under a 1.8-V power supply or 3 pJ/ bit.
|Number of pages||10|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - 4 Sep 2009|
- Low-voltage-differential-signaling (LVDS) driver
- Simultaneous switching noise (SSN)