Design of a power-reduction Viterbi decoder for WLAN applications

Chien Ching Lin*, Yen Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

55 Scopus citations

Abstract

In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access can be reduced by taking advantage of locality. Moreover, a low complexity compare-select-add unit is also presented, leading to save 15% area and 14.3% power dissipation as compared to conventional add-compare-select design. A test chip has been designed and implemented in 0.18-μ standard CMOS process. The test results show that 30 ∼ 40% power dissipation can be reduced, and the power efficiency reaches 0.75 mW per Mb/s at 6 Mb/s and 1.26 mW per Mb/s at 54 Mb/s as specified in IEEE 802.11a.

Original languageEnglish
Pages (from-to)1148-1156
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume52
Issue number6
DOIs
StatePublished - 1 Jun 2005

Keywords

  • Add-compare-select
  • Path merging
  • Path prediction
  • Survivor memory
  • Viterbi decoder

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