Design of a lower-error fixed-width multiplier for speech processing application

Lan-Da Van*, Shuenn Shyang Wang, Shing Tenqchen, Wu Shiung Feng, Bor Shenn Jeng

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Scopus citations

Abstract

A lower-error and lower-variance n × n multiplier is suitably proposed for VLSI design. Considering next lower significant stage in Pn-1 column and useful error-compensation model in the least significant part, and utilizing a near optimized index to classify the error terms are our strategies in order to achieve lower error and variance as compared with previously proposed structure in the subproduct-array of Baugh-Wooley algorithm. This novel structure applied to the fixed-width low-pass digital FIR filter for speech signal processing system has excellent performance in reducing maximum error, average error, and variation of errors as shown in given tables and figures.

Original languageEnglish
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Pages130-133
ISBN (Print)0780354710
DOIs
StatePublished - 1 Jan 1999
EventProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA
Duration: 30 May 19992 Jun 1999

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume3
ISSN (Print)0271-4310

Conference

ConferenceProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
CityOrlando, FL, USA
Period30/05/992/06/99

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