Design of a half-pixel precision motion estimation processor based on semi-systolic array architecture

Hong Zen Huang*, Chen-Yi Lee

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a VLSI architecture and chip design of a half-pixel precision motion estimation (ME) processor which meets the requirements defined in MPEG2 MPML. The proposed architecture is based on semi-systolic array (SSA) architecture which mainly contains stream memory, processor element (PE) array, parallel adder tree, and compare-and-select unit. This SSA-based ME architecture not only minimizes I/O bandwidth to reduce I/O pin-count and internal memory space, but also provides cost-effective computational power to meet real-time performance. Moreover, the proposed architecture makes it easy to integrate both integer unit (IU) and half-pixel unit (HU). Based on 0.8 μm CMOS SPDM process, the complete half-pixel ME processor with search range of [-16.5..+15.5] can be integrated on 81.74 mm2 silicon area. Test results show that clock speed up to 100 MHz can be achieved, implying that about 105 motion vectors per second can be obtained to meet the real-time requirements of MPEG2 MPML.

Original languageEnglish
Pages (from-to)35-45
Number of pages11
JournalJournal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an
Volume5
Issue number1
StatePublished - 1 Feb 1998

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