A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18μm CMOS . The key design issues involved in this advanced IC are discussed, including improving area and power efficiency. Power dissipation is greatly lowered through the architectural exploration. Measurement results show that MPEG-2 and H.264/AVC real-time decoding of QCIF@15fps are achieved at 1.15MHz with power dissipation of 108μW and 125μW respectively at 1V supply voltage.
|Title of host publication||2006 43rd ACM/IEEE Design Automation Conference, DAC'06|
|Number of pages||2|
|State||Published - 1 Dec 2006|
|Name||Proceedings - Design Automation Conference|