This paper presents a 10-bit SAR ADC operating at a supply voltage (VDD) from 0.200 to 0.250 V. In the proposed ADC structure, the positive input of the comparator is fixed at VDD to bias the comparator's input transistor pair with a sufficient gate-to-source voltage at such a low VDD. We propose an ultra-low VDD temperature-compensated bias generator to bias the comparator for addressing the severe temperature-dependent issue of the MOSFETs in the comparator, which operate in the deep subthreshold region. Detailed circuit analysis and derivation of design requirements are presented. A double-boosted and low-leakage sampling switch is also proposed to alleviate the severe leakage issue at low sampling rates. A test chip has been designed and fabricated in 180-nm CMOS. The ADC core occupies only 0.024 mm 2 . Measurement results show that the ADC achieves stable performance in the VDD range. At 0.225 V, the DNL and INL are within +1.04/-0.66 and +0.97/-1.04 LSB in the rail-to-rail input range, respectively. The measured peak SNDR at the Nyquist input frequency is 49.2 dB at 450 S/s. The whole ADC totally consumes 0.85 nW at 0.225 V including circuit leakages. The sub-nW power consumption makes it well suited for self-sustainable Internet-of-Things applications.
|Number of pages||13|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|State||Published - 1 May 2019|
- Sub-threshold operation
- low power/low voltage analog circuits