Design of 2×VDD logic gates with only 1×V DD devices in nanoscale CMOS technology

Po Yen Chiu, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The novel 2×VDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×V DD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×VDD tolerant capability. Thus, the new 2×VDD logic gates can be operated under 2×VDD voltage environment without suffering the gate-oxide reliability issue.

Original languageEnglish
Title of host publicationProceedings - IEEE 26th International SOC Conference, SOCC 2013
PublisherIEEE Computer Society
Pages33-36
Number of pages4
ISBN (Print)9781479911660
DOIs
StatePublished - 1 Jan 2013
Event26th IEEE International System-on-Chip Conference, SOCC 2013 - Erlangen, Germany
Duration: 4 Sep 20136 Sep 2013

Publication series

NameInternational System on Chip Conference
ISSN (Print)2164-1676
ISSN (Electronic)2164-1706

Conference

Conference26th IEEE International System-on-Chip Conference, SOCC 2013
CountryGermany
CityErlangen
Period4/09/136/09/13

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  • Cite this

    Chiu, P. Y., & Ker, M-D. (2013). Design of 2×VDD logic gates with only 1×V DD devices in nanoscale CMOS technology. In Proceedings - IEEE 26th International SOC Conference, SOCC 2013 (pp. 33-36). [6749656] (International System on Chip Conference). IEEE Computer Society. https://doi.org/10.1109/SOCC.2013.6749656