Design of 2 \times {\rm V}\rm DD-Tolerant I/O Buffer with PVT Compensation Realized by only 1 \times {\rm V}\rm DD Thin-Oxide Devices

Ming-Dou Ker, Po Yen Chiu

Research output: Contribution to journalArticlepeer-review

21 Scopus citations

Abstract

A new 2\times {\rm V}\rm DD-tolerant input/output (I/O) buffer with process, voltage, and temperature (PVT) compensation is proposed and verified in a 90-nm CMOS process. Consisting of the dynamic source bias and gate controlled technique, the proposed mixed-voltage I/O buffer realized by only 1 {\rm xV}\rm DD devices can successfully transmit and receive 2\times {\rm V}\rm DD signal. Utilizing this technique with only 1 {\rm xV}\rm DD devices, the digital logic gates are also modified to have 2 {\rm xV}\rm DD-tolerant capability. With2 {\rm xV} \rm DD-tolerant logic gates, the PVT variation detector has been implemented to detect PVT variations from $2\times {\rm V} \rm DD signal and provide compensation control to the 2\times {\rm V}\rm DD-tolerant I/O buffer without suffering the gate-oxide overstress issue.

Original languageEnglish
Article number6609128
Pages (from-to)2549-2560
Number of pages12
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume60
Issue number10
DOIs
StatePublished - 7 Oct 2013

Keywords

  • Gate-oxide overstress
  • mixed-voltage I/O buffer
  • process
  • voltage and temperature (PVT) variation

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