Design migration from peripheral ASIC design to area-io flip-chip design by chip I/O planning and legalization

Chia Yi Chang*, Hung-Ming Chen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Due to higher I/O count and power delivery problem in deep submicron (DSM) regime, flip-chip technology, especially for area-array architecture, has provided more oppertunities for adoption than traditional peripheral bonding design style in high-performance ASIC and microprocessor designs. However it is hard to tell which technique can provide better design cost edge in usually-Concerned perspectives. In this paper, we present a methodology to convert a previous peripheral bonding design to an area-IO flip-chip design. It is based on I/O buffer modeling and I/O planning algorithm to legalize I/O buffer blocks With core placement without sacrificing much of the previous optimization in the original core placement, The experimental results have shown that we have acheived better area and I/O wirelength in area-IO flip-chip style; compared With peripheral bonding style in packaging consideration.

Original languageEnglish
Title of host publication2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers
Pages147-150
Number of pages4
DOIs
StatePublished - 1 Oct 2007
Event2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Hsinchu, Taiwan
Duration: 26 Apr 200728 Apr 2007

Publication series

Name2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Conference

Conference2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006
CountryTaiwan
CityHsinchu
Period26/04/0728/04/07

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    Chang, C. Y., & Chen, H-M. (2007). Design migration from peripheral ASIC design to area-io flip-chip design by chip I/O planning and legalization. In 2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers (pp. 147-150). [4027518] (2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers). https://doi.org/10.1109/VDAT.2006.258146