Design in hot-carrier reliability for high performance logic applications

Peng Fang*, Jiang Tao, Jone F. Chen, Chen-Ming Hu

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

31 Scopus citations

Abstract

Static (DC) and dynamic (AC) hot carrier degradation mechanisms were reviewed. Circuit performance degradation has been correlated to individual NMOS or PMOS device under DC stress. AC degradation model calibration and evaluation guidelines were also reviewed to ensure the use of hot-carrier reliability simulation tools in circuit level. As an example, thousand-hour inverter ring oscillator speed degradation data with different fanout, stress voltages, channel length, and processes are compared with that obtained from reliability simulation. The results show that reliability simulation is a powerful tool for logic circuit design optimization. It can predict the long-term circuit hot-carrier degradation accurately. The reliability of inverter, NAND, and NOR structures are also simulated and compared.

Original languageEnglish
Pages (from-to)525-531
Number of pages7
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - 1 Jan 1998
EventProceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA
Duration: 11 May 199814 May 1998

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