A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFET’s is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2D analytical model is developed for the electric field in the gate-to-drain overlap region. This model successfully explains the observed GIDL dependence on the lateral doping profile of the drain. Also, a technique is proposed for extracting this lateral doping profile using the measured dependence of GIDL current on the applied substrate bias. Finally, the GIDL current is found to be much smaller in lightly doped LDD devices than in SD or fully overlapped LDD devices, due to smaller vertical and lateral electric fields. However, as the phosphorus dose approaches 1014/cm2, the LDD and fully overlapped LDD devices exhibit similar GIDL current.